1. Field of the Invention
The present invention relates to a semiconductor memory device, and specifically, to the layout of each element in a memory cell in a semiconductor memory device.
2. Description of the Background Art
Conventionally, DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) are known as semiconductor memory devices.
DRAM is a semiconductor memory device having memory cells each configured with one MOS (Metal Oxide Semiconductor) transistor and one capacitor. Since such a simple configuration of memory cells is suitable for achieving higher integration and larger capacity of a semiconductor device, it is used for various electronic equipment.
SRAM usually includes two access MOS transistors, two driver MOS transistors, and two load MOS transistors or resistance elements. The exemplary configuration of a memory cell of SRAM is disclosed in, for example, Japanese Patent Laying-Open Nos. 6-291281, 7-161840, 62-257698.
Pseudo-SRAM is also known, which uses memory cells of DRAM and has the same interface as SRAM.
In DRAM, however, a refresh operation is necessary to retain memory, and a writing/reading operation to/from a memory cell being refreshed can not be performed. Accordingly, during a refresh operation of a memory cell, writing/reading operation for that memory cell must be stopped temporarily until the refresh operation is completed. Further, since a large amount of current is consumed for the refresh operation, the data retention time is shorter than SRAM when the stored contents are retained by a battery or the like.
As for SRAM, though the refresh operation is not necessary, the occupying area of one memory cell is larger than DRAM, since the number of elements forming one memory cell, such as MOS transistors, is larger. Accordingly, it is difficult to attain a large capacity, and the cost per one bit (per-bit cost) is higher than DRAM.
On the other hand, pseudo-SRAM is capable of attaining a large capacity, since it employs DRAM memory cells, but it still requires the refresh operation. The refresh operation from the outside can be eliminated if a self-refresh function is employed, but the refresh operation must be performed during writing and reading operations. As such, the period for writing and reading operations and the period for the refresh operation are included in one cycle, and hence the cycle time becomes longer than in a normal SRAM. Additionally, since a refresh current flows, current consumption will become larger than in a normal SRAM, and hence the data retention period of the battery will become shorter.